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MDT10P74
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power consumption and high noise immunity. On chip memory includes 4K words of ROM, and 192 bytes of static RAM. u u -Port B<7:4> interrupt on change -CCP1, CCP2, SCM, USAR, USAT, PCM A/D converter module: -8 analog inputs multiplexed into one A/D converter -8-bit resolution TMR0 : 8-bit real time clock/counter TMR1 : 16-bit real time clock/count
2. Features
u The followings are some of the features on the hardware and software : u u u u Fully CMOS static design 8-bit data bus On chip EPROM size : 4.0 K words Internal RAM size : 238 bytes (192 general purpose registers, 46 special registers) u u u u 37 single word instructions 14-bit instructions 8-level stacks Operating voltage : 2.5 V ~ 5.5 V (PRD Disable) 4.5 V ~ 5.5 V (PRD Enable) u u Operating frequency : DC ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u Addressing modes include direct, indirect and relative addressing modes u u u u u u u Power-on Reset Power edge-detector Reset Power range-detector Reset Sleep Mode for power saving Capture, Compare, PWM module Synchronous serial port with SCM 12 interrupt sources: -External INT pin -TMR0 timer, TMR1 timer, TMR2 timer -A/D conversion completion u u
TMR2 : 8-bit clock/counter(internal) 4 types of oscillator can be selected by programming option: RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator On-chip RC oscillator based Watchdog Timer(WDT) 33 I/O pins with their own independent direction control
3. Applications
The application areas of this MDT10P74 range from appliance motor control and high speed auto-motive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote
controller, small instruments, chargers, toy, automobile and PC peripheral ... etc.
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P. 1
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
4. Pin Assignment
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P. 2
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
5. Pin Function Description
Pin Name PA0~PA3, PA5 RTCC/PA4 I/O I/O I/O Function Description Port A, TTL input level / Analog input channel Real Time Clock/Counter, Schmitt Trigger input levels Open drain output PB0~PB7 I/O Port B, TTL input level / PB0:External interrupt input , PB4~PB7:Interrupt on pin change PC0~PC7 PD0~PD7 PE0~PE2 I/O I/O I/O Port C, Schmitt Trigger input levels Port D, Schmitt Trigger input levels / TTL input level Port E, Schmitt Trigger input levels / TTL input level , Analog input channel /MCLR OSC1/CLKIN OSC2/CLKOUT I I O Master Clear, Schmitt Trigger input levels Oscillator Input/external clock input Oscillator Output/in RC modeA the CLKOUT pin has 1/4 frequency of CLKIN Vdd Vss Power supply Ground
6. Memory Map
(A) Register Map Address BANK0 00 01 02 03 04 05 06 07 08 09 0A Indirect Addressing Register RTCC PCL STATUS MSR Port A Port B Port C Port D Port E PCHLAT Description
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P. 3
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
Address 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20~7F BANK1 01 05 06 07 08 09 0C 0D 0E TMR CPIO A CPIO B CPIO C CPIO D CPIO E PIEB1 PIEB2 PSTA INTS PIFB1 PIFB2 TMR1L TMR1H T1STA TMR2 T2STA SCMBUF SCMCTL CCP1L CCP1H CCP1CTL RCSC TXREG RCREG CCP2L CCP2H CCP2CTL ADRES ADS0 General purpose register Description
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P. 4
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
Address 12 14 18 19 1F A0~FF T2PER SCMSTA TXSC BRREG ADS1 General purpose register Description
(1)IAR (Indirect Address Register) G R00 (2)RTCC (Real Time Counter/Counter Register) G R01 (3) PC (Program Counter) G R02,R0A Write PC --- from PCHLAT Write PC --- from PCHLAT LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK
A11
A10~A8
A7~A0
Write PC --- from ALU LJUMP, LCALL --- from instruction word RTWI, RET, RTFI --- from STACK
(4) STATUS (Status register) G R03
Bit
0 1 2 3 4 5
Symbol
C HC Z /PF /TF RBS0 Carry bit Half Carry bit Zero bit
Function
Power down Flag bit WDT Timer overflow Flag bit Register Bank Select bit G 0 G 00H --- 7FH(Bank0) 1 G 80H --- FFH(Bank1)
7-6
XX
General purpose bit
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P. 5
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
(5) MSR (Memory Bank Select Register) G R04 Memory Bank Select Register G 0 G 00~7F(Bank0) 1 G 80~FF(Bank1)
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode (6) PORT A G R05 PA5~PA0, I/O Register (7) PORT B G R06 PB7~PB0, I/O Register (8) PORT C G R07 PC7~PC0, I/O Register (9) PORT D G R08 PD7~PD0, I/O Register (10) PORT E G R09 PE2~PE0, I/O Register (11)PCHLAT G R0A
(12) INTS (Interrupt Status Register) G R0B
Bit 0 1 2 3
Symbol RBIF INTF TIF RBIE
Function PORT B change interrupt flag. Set when PB <7G inputs change 4> Set when INT interrupt occurs. INT interrupt flag. Set when TMR0 overflows. 0 G disable PB change interrupt 1 G enable PB change interrupt
4
INTS
0 G disable INT interrupt 1 G enable INT interrupt
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P. 6
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
Bit 5 Symbol TIS 0 G disable TMR0 interrupt 1 G enable TMR0 interrupt 6 PEIE 0 G disable all peripheral interrupt 1 G enable all peripheral interrupt 7 GIS 0 G disable global interrupt 1 G enable global interrupt (13) PIFB1 (Peripheral Interrupt Flag Bit) G R0C Bit 0 Symbol TMR1IF TMR1 interrupt flag 0 G TMR1 did not overflow 1 G TMR1 overflowed 1 TMR2IF TMR2 interrupt flag 0 G No TMR2 to T2PER match occurred 1 G TMR2 to T2PER match occurred 2 CCP1IF CCP1 interrupt flag 0 G No TMR1 capture/compare occurred 1 G A TMR1 capture/compare occurred 3 SCMIF SCM interrupt flag 0 G Waiting SCM transmit/receive 1 G The SCM transmission/reception is complete 4 TXIF USART transmit interrupt flag 0 G The USART transmit buffer is full 1 G The USART transmit buffer is empty 5 RCIF UASRT receive interrupt flag 0 G The USART receive buffer is empty 1 G The USART receive buffer is full 6 ADIF A/D interrupt flag 0 G A/D conversion is not complete 1 G A/D conversion completed 7 PCMIF PCM read/write interrupt flag 0 G No read or write has occurred 1 G A read or a write has occurred Function Function
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P. 7
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
(14) PIFB2 (Peripheral Interrupt Flag Bit) G R0D Bit 0 Symbol CCP2IF CCP2 interrupt flag 0 G No TMR1 capture/compare occurred 1 G A TMR1 capture/compare occurred 7~1 -Unimplemented Function
(15) TMR1L G R0E The LSB of the 16-bit TMR1 (16) TMR1H G R0F The MSB of the 16-bit TMR1 (17) T1STA G R10
Bit 0
Symbol TMR1ON 0 G Stop TMR1 1 G Enable TMR1
Function
1
TMR1CLK
0 G Internal clock (Fosc/4) 1 G External clock from pin PC0
2
/T1SYNC
TMR1CLK = 1 0 G Synchronize external clock 1 G Do not synchronize external clock TMR1CLK = 0 This bit is ignored
3
T1OSCEN
0 G TMR1 Oscillator is shut off 1 G TMR1 Oscillator is enable
5~4
T1CKPS1 ~ T1CKPS0
1 1 = 1G Prescale value 8 1 0 = 1G Prescale value 4 0 1 = 1G Prescale value 2 0 0 = 1G Prescale value 1
7~6
--
Unimplemented
(18) TMR2 G R11 TMR2 register
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P. 8
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
(19) T2STA G R12
Bit 1~0
Symbol T2CKPS1 ~ T2CKPS0 0 0 = Prescaler is 1 0 1 = Prescaler is 4 1 x = Prescaler is 16 0 G TMR2 is off 1 G TMR2 is on
Function
2
TMR2ON
7~3
--
Unimplemented
(20) SCMBUF G R13 Serial communication port buffer
(21) SCMCTL G R14
Bit 3~0
Symbol SCM3 ~ SCM0
Function 0 0 0 0 G SCM master mode , clock = Fosc/4 0 0 0 1 G SCM master mode , clock = Fosc/16 0 0 1 0 G SCM master mode , clock = Fosc/64 0 0 1 1 G SCM master mode , clock = TMR2 output/2 0 1 0 0 G SCM slave mode , clock = SCK pin , /SS control enable 0 1 0 1 G SCM slave mode , clock = SCK pin , /SS control disable
4
CKS
0 G Transmit happens on rising edge , receive on falling edge, Idle state for clock is low level. 1 G Transmit happens on falling edge , receive on rising edge, Idle state for clock is high level
5
SCMEN
0 G disable SCM, then PC3, PC4, PC5 is I/O port. 1 G enable SCM
6
SCMROI
0 G No overflow 1 G Overflow
7
WCOL
0 G No collision 1 G The SCMBUF is written while it is still transmitting the previous word
(22) CCP1L G R15 Capture/Compare/PWM LSB
(23) CCP1H G R16 Capture/Compare/PWM MSB This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 9
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
(24) CCP1CTL G R17
Bit 3~0
Symbol CCP1M3 ~ CCP1M0 0 0 0 0 G CCP1 off
Function
0 1 0 0 G Capture1 mode , every falling edge 0 1 0 1 G Capture1 mode , every rising edge 0 1 1 0 G Capture1 mode , every 4th rising edge 0 1 1 1 G Capture1 mode , every 16th rising edge 1 0 0 0 G Compare1 mode , set output on match 1 0 0 1 G Compare1 mode , clear output on match 1 0 1 0 G Compare1 mode , generate software interrupt on match 1 0 1 1 G Compare1 mode , trigger special event 1 1 x x G PWM1 mode
5~4 7~6
PWM1LSB These bits are the two LSBs of the PWM1 duty cycle -Unimplemented
(25) RCSC G R18
Bit 0 1
Symbol RX9DF OERF 9th bit of received data 0 G No overrun error 1 G Overrun error
Function
2
FERF
0 G No framing error 1 G Framing error
3 4
-CRENF
Unimplemented 0 G Disable continuous receive 1 G Enable continuous receive
5
SRENF
0 G Disable single receive 1 G Enable single receive
6
RX9ENF
0 G Select 8-bit reception 1 G Select 9-bit reception
7
SPENF
0 G Serial port disable 1 G Serial port enable
(26) TXREG G R19 USART transmit register (27) RCREG G R1A USART receive register This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 10
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
(28) CCP2L G R1B Capture/Compare/PWM LSB
(29) CCP2H G R1C Capture/Compare/PWM MSB
(30) CCP2CTL G R1D Bit 3~0 Symbol CCP2M3 ~ CCP2M0 0 0 0 0 G CCP2 off 0 1 0 0 G Capture2 mode , every falling edge 0 1 0 1 G Capture2 mode , every rising edge 0 1 1 0 G Capture2 mode , every 4th rising edge 0 1 1 1 G Capture2 mode , every 16th rising edge 1 0 0 0 G Compare2 mode , set output on match 1 0 0 1 G Compare2 mode , clear output on match 1 0 1 0 G Compare2 mode , generate software interrupt on match 1 0 1 1 G Compare2 mode , trigger special event 1 1 x x G PWM2 mode 5~4 7~6 PWM2LSB These bits are the two LSBs of the PWM2 duty cycle -Unimplemented Function
(31) ADRES G R1E A/D result register
(32) ADS0 G R1F Bit 0 Symbol ADRUN Function 0 G A/D converter module is shut off and consumes no operating current 1 G A/D converter module is operating 1 2 -GO/DONEB Unimplemented 0G A/D conversion not in progress 1G A/D conversion in progress 5~3 CHS2~0 000 G AIC0 001 G AIC1 010 G AIC2 011 G AIC3 100 G AIC4 101 G AIC5 110 G AIC6 111 G AIC7 7~6 ASCS1-0 00 G fosc/2 01G fosc/8 10 G fosc/32 11 G f RC (*Note)
*NoteG determined by OSC mode, HFG fosc/32 XTG fosc/8 RCG fosc/2 LFG fosc/2 (33) TMR (Time Mode Register) G R81 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 11
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
Bit Symbol Prescaler Value 000 001 010 011 2~0 PS2~0 100 101 101 111 Function RTCC rate 1 G 2 1 G 4 1 G 8 1 G 16 1 G 32 1 G 64 1 G 128 1 G 256 3 PSC Prescaler assignment bit G 0 X RTCC 1 X Watchdog Timer RTCC signal edge G 0 X Increment on low-to-high transition on RTCC pin 1 X Increment on high-to-low transition on RTCC pin RTCC signal set G 0 X Internal instruction cycle clock 1 X Transition on RTCC pin Interrupt edge select 0 X Interrupt on falling edge on PB0 1 X Interrupt on rising edge on PB0 PORTB3~0 pull-hi 0 X PORTB3~0 pull-hi are enable 1 X PORTB3~0 pull-hi are disable WDT rate 1 G 1 1 G 2 1 G 4 1 G 8 1 G 16 1 G 32 1 G 64 1 G 128
4
TCE
5
TCS
6
IES
7
PBPH
(34) CPIO A (Control Port I/O Mode Register) G R85 x"0", I/O pin in output mode; x"1", I/O pin in input mode. (35) CPIO B (Control Port I/O Mode Register) G R86 x"0", I/O pin in output mode; x"1", I/O pin in input mode. (36) CPIO C (Control Port I/O Mode Register) G R87 x"0", I/O pin in output mode; x"1", I/O pin in input mode. (37) CPIO D (Control Port I/O Mode Register) G R88 x"0", I/O pin in output mode; x"1", I/O pin in input mode.
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P. 12
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
(38) CPIO E (Control Port I/O Mode Register) G R89 Bit Symbol Function
2~0 BIT 2 ~ BIT 0 Port E control port I/O mode bits 0 G I/O pin in output mode 1 G I/O pin in input mode 3 4 -Unimplemented
PCMMODE PCM mode select bit 0 G General I/O mode 1 G PCM mode
5
IBOV
Input buffer overflow detect bit 0 G No overflow occurred 1 G Overflow
6
OBF
Output buffer full status bit 0 G The output buffer has been read 1 G The output buffer has not been read
7
IBF
Input buffer full status bit 0 G No word has been received 1 G A word has been received
(39) PIEB1 G R8C Bit 0 Symbol TMR1IE TMR1 interrupt enable bit 0 G disable TMR1 interrupt 1 G enable TMR1 interrupt 1 TMR2IE TMR2 interrupt enable bit 0 G disable TMR2 interrupt 1 G enable TMR2 interrupt 2 CCP1IE CCP1 interrupt enable bit 0 G disable CCP1 interrupt 1 G enable CCP1 interrupt 3 SCMIE SCM interrupt enable bit 0 G disable SCM interrupt 1 G enable SCM interrupt 4 TXIE USART transmit interrupt enable bit 0 G disable the USART transmit interrupt 1 G enable the USART transmit interrupt Function
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P. 13
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
Bit 5 Symbol RCIE Function USART receive interrupt enable bit 0 : disable the USART receive interrupt 1 : enable the USART receive interrupt 6 ADIE A/D interrupt enable bit 0 : disable A/D interrupt 1 : enable A/D interrupt 7 PCMIE PCM R/W interrupt enable bit 0 : disable the PCM interrupt 1 : enable the PCM interrupt (40) PIEB2 : R8D Bit 0 Symbol CCP2IE 0G disable CCP2 interrupt 1G enable CCP2 interrupt 7~1 (41) PSTA : R8E Bit 0 1 Symbol PRDB PORB 0:Power range-detector Reset occurred 1:No Power range-detector Reset Occurred 0:Power on Reset occurred 1:No Power on Reset occurred (42) T2PER : R92 Timer2 period (43) SCMSTA : R94 Bit 0 Symbol BF 0 : Receive not complete 1 : Receive complete 7~1 (44) TXSC : R98 Bit 0 1 Symbol TX9DF TSRCF 9th bit of transmit data 0 : TSR full 1 : TSR empty 2 HBRCF 0 : Low speed 1 : High speed This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw Function -Unimplemented Function Function -Unimplemented Function
P. 14
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
Bit 3 4 Symbol -UMSF Unimplemented 0 : USART asynchronous mode 1 : USART synchronous mode 5 TXENF 0 : Transmit disable 1 : Transmit enable 6 TX9ENF 0 : Select 8-bit reception 1 : Select 9-bit reception 7 CSSF 0 : Slave mode 1 : Master mode Function
(45) BRREG : R99 Baud rate register (46) ADS1 ( A/D Status Register ) : R9F Bit Symbol Function 0 0 0 : PA0~3, PA5, PE0~2 = analog input, VREF = VDD 2~0 PAVM2~0 0 0 1 : PA0~2, PA5, PE0~2 = analog input, VREF = PA3 0 1 0 : PA0~3, PA5 = analog input, PE0~2 = digital I/O, VREF = VDD 0 1 1 : PA0~2, PA5 = analog input, PE0~2 = digital I/O, VREF = PA3 1 0 0 : PA0, 1, 3 = analog input, PA2, 5, PE0~2 = digital I/O, VREF = VDD 1 0 1 : PA0, 1 = analog input, PA2, 5, PE0~2 = digital I/O, VREF =PA3 1 1 x : PA0~3, 5, PE0~2 = digital I/O 7~3 -Unimplemented
(47) Configurable options for EPROM (Set by writer) :
Oscillator Type RC Oscillator
HFXT Oscillator XTAL Oscillator LFXT Oscillator
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
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P. 15
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
Power-range control Power-range disable Power-range enable
Oscillator-start Timer control 0ms 75ms
Power-edge Detect PED Disable PED Enable (B) Program Memory Address 000-FFF 000 004 Program memory
Security state Security Disable Security Enable
Description
The starting address of power on, external reset or WDT time-out reset. Interrupt vector
7. Reset Condition for all Registers
Register Address Power-On Reset, Power range detector Reset N/A xxxx xxxx 0000 0000 0000 0001 1xxx xxxx xxxx --xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---- -xxx ---0 0000 /MCLR or WDT Reset Wake-up from SLEEP
IAR RTCC PC STATUS MSR PORT A PORT B PORT C PORT D PORT E PCHLAT
00h 01h 0Ah,02h 03h 04h 05h 06h 07h 08h 09h 0Ah
N/A uuuu uuuu 0000 0000 0000 000# #uuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu ---0 0000
N/A uuuu uuuu PC+1 000# #uuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu ---u uuuu
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 16
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
Register Address Power-On Reset, Power range detector Reset 0000 000x 0000 0000 ---- ---0 xxxx xxxx xxxx xxxx --00 0000 0000 0000 ---- -000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 -00x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 1111 1111 0000 -111 0000 0000 ---- ---0 ---- --0u 1111 1111 /MCLR or WDT Reset Wake-up from SLEEP
INTS PIFB1 PIFB2 TMR1L TMR1H T1STA TMR2 T2STA SCMBUF SCMCTL CCP1L CCP1H CCP1CTL RCSC TXREG RCREG CCP2L CCP2H CCP2CTL ADRES ADS0 TMR CPIOA CPIOB CPIOC CPIOD CPIOE PIEB1 PIEB2 PSTA T2PER
0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 81h 85h 86h 87h 88h 89h 8Ch 8Dh 8Eh 92h
0000 000u 0000 0000 ---- ---0 uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 ---- -uuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0000 0000 -00x 0000 0000 0000 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 1111 1111 0000 -111 0000 0000 ---- ---0 ---- --uu 1111 1111
uuuu uuuu uuuu uuuu ---- ---u uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uu-u uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu ---- ---u ---- --uu 1111 1111
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 17
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
Register Address Power-On Reset, Power range detector Reset ---- ---0 0000 -010 0000 0000 ---- -000 /MCLR or WDT Reset Wake-up from SLEEP
SCMSTA TXSC BRREG ADS1
94h 98h 99h 9Fh
---- ---0 0000 -010 0000 0000 ---- -000
---- ---u uuuu -uuu uuuu uuuu ---- -uuu
Note : uxunchanged, xxunknown, - xunimplemented, read as "0" #xvalue depends on the condition of the following table
Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Power-on reset Power-range reset
Status: bit 4 u 1 0 0 1 1
Status: bit 3 u 0 1 0 1 1
PSTA: bit 1 u u u u 0 u
PSTA: bit 0 u u u u x 0
Note : uxunchanged, xxunknown, - xunimplemented, read as "0"
8. Instruction Set :
Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO R STWR R LDR R, t LDWI I SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return from subroutine Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register Increment register, skip if zero Add W and register
Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr
Function None
Operating
Status
0/WT 0/WT, stop OSC W/TMODE Stack/PC W/CPIO r W/R R/t I/W [R(0~3) R(4~7)]/t R + 1/t R + 1/t W + R/t
TF, PF TF, PF None None None None Z None None Z None C, HC, Z
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P. 18
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
Instruction Code 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 100nnn nnnnnnnn 101nnn nnnnnnnn 110111 iiiiiiii 110001 iiiiiiii 111000 iiiiiiii 010000 00001001 Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive `a' Exclusive `o' Logic AND `a' b t : : 0 1 : : : : : : : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Mnemonic Operands SUBWR R, t DECR R, t DECRSZ R, t ANDWR R, t ANDWI i IORWR R, t IORWI i XORWR R, t XORWI i COMR R, t RRR RLR CLRW CLRR BCR BSR R R, b R, b R, t R, t Function Subtract W from register Decrement register Operating Status
R W/t or (R+/W+1 C, HC, Z /t) R 1/t Z None Z Z Z Z Z Z Z C C Z Z None None None None None None C,HC,Z None C,HC,Z None
Decrement register, skip if zero R 1/t AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Add immediate to W Return, place immediate to W Subtract W from immediate Reture from interrupt R a W/t i a W/W R a W/t i a W/W R o W/t i o W/W /R/t R(n) /R(n-1), C/R(7), R(0)/C R(n)/r(n+1), C/R(0), R(7)/C 0/W 0/R 0/R(b) 1/R(b) Skip if R(b)=0 Skip if R(b)=1 n/PC, PC+1/Stack n/PC W+i/W Stack/PC,i/W i-W/W Stack/PC,1/GIS
BTSC R, b BTSS R, b LCALL n LJUMP n ADDWI i RTWI i
SUBWI i RTFI
R C HC Z / x i
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P. 19
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
n : Immediate address
9. Electrical Characteristics
*Note: Temperature=25C 1.Operation Current : (1) HF (C=10p) , WDT - disable, PRD - disable 4M 2.5V 3.0V 4.0V 5.0V 5.5V 330u 480u 720u 1.4m 1.8m 10M 710u 910u 1.4m 2.6m 3.5m 20M 1.3m 1.7m 2.8m 4.3m 5.7m Sleep <1u <1u <1u <1u <1u
These parameters are for reference only.
(2) XT (C=10p) , WDT - disable, PRD - disable 1M 2.5V 3.0V 4.0V 5.0V 5.5V 100u 220u 310u 560u 780u 4M 310u 450u 660u 1.0m 1.5m 10M 600u 860u 1.3m 1.9m 2.9m Sleep <1u <1u <1u <1u <1u
These parameters are for reference only.
(3) LF (C=10p) , WDT - disable, PRD - disable, 32K 2.5V 3.0V 4.0V 5.0V 5.5V 10u 15u 25u 40u 80u 455K @2.7V 50u 60u 80u 140u 250u 1M 80u 90u 150u 230u 390u Sleep <1u <1u <1u <1u <1u
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 20
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
(4) RC, WDT - disable; PRD - disable; @Vdd = 5.0V C R 4.7k 10k 3p 47k 100k 300k 470k 4.7k 10k 20p 47k 100k 300k 470k 4.7k 10k 100p 47k 100k 300k 470k 4.7k 10k 300p 47k 100k 300k 470k Freq. 8.4M 4.5M 1.1M 520K 180K 110K 3.2M 2.2M 500K 240K 81.2K 51.6K 1.4M 688K 152K 72.8K 24.4K 15.6K 592K 292K 64K 30.8K 10.4K 6.4K Current 1.7m 1.1m 430u 330u 165u 155u 1.3m 640u 230u 180u 150u 145u 500u 370u 165u 150u 140u 138u 350u 190u 147u 141u 137u 136u
These parameters are for reference only.
2. Input Voltage (Vdd = 5V) : Port Vil TTL Schmitt trigger Vih TTL Schmitt trigger Min Vss Vss 3.0V 3.8V Max 0.8V 0.6V Vdd Vdd
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 21
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
Input Voltage (Vdd = 3V) : Port Vil TTL Schmitt trigger Vih TTL Schmitt trigger Min Vss Vss 2.0V 2.6V Max 0.4V 0.2V Vdd Vdd
These parameters are for reference only.
3. Output Voltage (Vdd = 5V) : PA,PB Voh Vol Voh Vol 3.5V 0.9V 4.2V 0.7V Condition Ioh = -20mA Iol = 20mA Ioh = -5mA Iol = 5mA
These parameters are for reference only.
4. Output Current (Max.) (Vdd = 5V) : I/O Port source current sink current These parameters are for reference only. Current 25mA 40mA
5. The basic WDT time-out cycle time : Time 2.5V 3.0V 4.0V 5.0V 5.5V 26 23 20 18 17 Unit = ms These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 22
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
6. PRD : (1)PRD reset voltage : Voltage Vih Vil 4.010% 3.610% Unit = V These parameters are for reference only.
(2) PRD reset current : Current 5.0V 4.0V 120 100 Unit = uA These parameters are for reference only.
7. Pull high resistor : Vdd PB3~0 Pull high 5V 40 3V 80
Unit = K Ohm These parameters are for reference only.
8. MCLR filter time : Vdd=5V time 640 Unit = ns These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 23
(Preliminary)
2005/6 Ver. 1.5
MDT10P74
10.Block Diagram
Stack 8 Levels
EPROM 4Kx14 (MDT10P74)
RAM 192X8
Po rtA PA A 0~P 5 its Port A 6b
12 bits 12 bits Program Counters 14 bits
Instruction Register
Special Register Po rtB PB B 0~P 7 Port B 8b its D0~D7
OSC 1 OSC M R 2 CL
Oscillator Circuit
Instruction Decoder
Control Circuit PortC
PortC PC0~PC7 8b its
Data 8-bit Power on Reset Power Down Reset Po er Ran e D to w g etec r A/D 8bit Working Register ALU Status Register PortD PortD PD0~PD7 8b its
Counter / Tim er0 Timer1 / Timer2 (CCP1,CCP2)
Parallel Slave Port / Serial Port (SCM/USART)
WDT/OST Tim er
PortE
P ortE PE0~PE2 3b its
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 24
(Preliminary)
2005/6 Ver. 1.5

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